WHAT DO YOU MEAN BY MACHINE INSTRUCTIONS?

A set of binary codes that are recognised and executed directly by a processor is called a machine code. An individual machine code is called a machine instruction.

Main memory holds machine instructions and data.

Fields of an Instruction:

• Opcode: The operation itself is usually represented by a code called the opcode.
• Address: Other than opcode, all the other parts of an instruction are called address or operand fields.
• Mode: It specifies the way the operand or effective address is determined. It may be implicit or explicit in the instruction.

Instruction Cycle

Instruction cycle describes the execution sequence of the program instruction contain two sub cycles:

• Fetch cycle
• Execution cycle

Fetch Cycle

• Objective of a fetch cycle is instruction fetch. In this process, CPU fetch the instruction from main memory based on program counter.

Execution Cycle

• Objective of a execution cycle is processing of an instruction.
• CPU organisation is classified in the three types based on the availability of “ALU operands”:
  1. Stack CPU
  2. Accumulator CPU
  3. General register CPU

# Stack CPU

• In this organization ALU operations are performed only on stack data means both of the operands are always required into stack.

# Accumulator CPU

• In this organisation, for ALU operation Ist operand is always required in the accumulator while 2nd operand may be present either in the register or in the memory.

# General register CPU

• Based on the number of registers possible in the CPU, architecture is divided into two categories:
  # Register to memory reference CPU.
  # Register to register reference CPU.

#Register to memory reference CPU:

1. In this architecture, number of registers are less in comparison with register to register reference CPU.
2. In this architecture, for performing ALU operation it is needed to store first operand in the register while second operand can either be in register/memory.
3. After processing, result is stored in the source 1 register.
4. Compatible instruction format: “2 address instruction”

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